preliminary 1,024k x 32 3.3v static ram module cym1851v33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05268 rev. ** revised march 15, 2002 851v33 features ? high-density 3.3v 32-megabit sram module 32-bit standard footprint supports densities from 16k x 32 through 1m x 32 high-speed srams ? access time of 12 ns low active power ? 3.3w (max.) at 12 ns 72 pins available in zip, simm, or angled simm format functional description the cym1851v33 is a 3.3v high-performance 32-megabit static ram module organized as 1,024k words by 32 bits. this module is constructed from eight 1,024k x 4 srams in soj packages mounted on an epoxy laminate substrate. four chip selects are used to independently enable the four bytes. read- ing or writing can be executed on individual bytes or any com- bination of multiple bytes through proper use of selects. the cym1851v33 is designed for use with standard 72-pin simm sockets. the pinout is downward compatible with the 64-pin jedec zip/simm module family (cym1821, cym1831, cym1836, and cym1841). thus, a single mother- board design can be used to accommodate memory depth ranging from 16k words (cym1821) to 1,024k words (cym1851). the cym1851v33 is offered in vertical and an- gled simm configurations and both are available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. presence detect pins (pd 0 ? pd 3 ) are used to identify module memory density in applications where modules with alternate word depths can be interchanged. a 0 -a 19 logic block diagram pin configuration oe i/o 0 ? i/o 3 cs 3 cs 1 20 4 4 4 4 4 4 4 4 cs 2 cs 4 i/o 8 ? i/o 11 i/o 16 ? i/o 19 i/o 24 ? i/o 27 pd 0 -gnd pd 1 -open pd 2 -gnd pd 3 -open we 1m x 4 sram 1m x 4 sram 1m x 4 sram 1m x 4 sram 1m x 4 sram 1m x 4 sram 1m x 4 sram 1m x 4 sram zip/simm top view nc a 4 pd 3 pd 2 pd 0 gnd i/o 0 pd 1 i/o 1 i/o 8 i/o 2 i/o 9 i/o 3 v cc a 7 i/o 11 i/o 10 a 0 i/o 6 gnd nc a 15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 i/o 7 we a 8 a 9 i/o 4 i/o 5 a 14 cs 1 cs 3 a 16 gnd i/o 16 i/o 17 a 12 a 13 i/o 20 i/o 21 i/o 22 i/o 14 i/o 15 a 1 a 2 i/o 12 i/o 13 cs 2 i/o 18 i/o 19 a 10 a 11 cs 4 a 17 oe i/o 24 i/o 25 v cc a 6 i/o 28 i/o 29 i/o 26 i/o 27 a 3 a 5 66 68 70 65 67 69 i/o 23 gnd a 19 i/o 30 i/o 31 a 18 72 71 nc nc i/o 4 ? i/o 7 i/o 12 ? i/o 15 i/o 20 ? i/o 23 i/o 28 ? i/o 31
cym1851v33 preliminary document #: 38-05268 rev. ** page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +125 c ambient temperature with power applied............................................... ? 10 c to +85 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state ................................................ ? 0.5v to +v cc dc input voltage............................................ ? 0.5v to +4.6v selection guide 1851v33-12 1851v33-15 1851v33-20 1851v33-25 1851v33-35 maximum access time (ns) 12 15 20 25 35 maximum operating current (ma) 1450 1250 1100 1100 1100 maximum standby current (ma) 540 520 480 480 480 shaded area contains advance information. operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v + 10%/ ? 5% electrical characteristics over the operating range parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 16 +16 a i oz output leakage current gnd < v o < v cc , output disabled ? 10 +10 a i cc v cc operating supply current v cc = max., i out = 0 ma, cs n < v il, f = f max -12 1450 ma -15 1250 ma -20, -25, -35 1100 ma i sb1 automatic cs power-down current [1] max. v cc , cs > v ih , min. duty cycle = 100% -12 540 ma -15 520 ma -20, -25, -35 480 ma i sb2 automatic cs power-down current [1] max. v cc , cs > v cc ? 0.2v, v in > v cc ? 0.2v, or v in < 0.2v 270 ma shaded area contains advance information. capacitance [2] parameter description test conditions max. unit c ina input capacitance (we , oe , a 0 ? 19 ) t a = 25 c, f = 1 mhz, v cc = 5.0v 40 pf c inb input capacitance (cs ) 10 pf c out output capacitance 8 pf notes: 1. a pull-up resistor to v cc on the cs input is required to keep the device deselected during v cc power-up, otherwise i sb will exceed values given. 2. tested on a sample basis.
cym1851v33 preliminary document #: 38-05268 rev. ** page 3 of 9 ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) 5ns 5 ns output r1 317 ? r1 317 ? r2 351 ? r2 351 ? 167 ? equivalent to: th venin equivalent 1.73v switching characteristics over the operating range [3] 1851v33-12 1851v33-15 parameter description min. max. min. max. unit read cycle t rc read cycle time 12 15 ns t aa address to data valid 12 15 ns t oha data hold from address change 3 3 ns t acs cs low to data valid 12 15 ns t doe oe low to data valid 7 8 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z 7 8 ns t lzcs cs low to low z [4] 3 3 ns t hzcs cs high to high z [4, 5] 7 8 ns t pd cs high to power-down 12 15 ns write cycle [6] t wc write cycle time 12 15 ns t scs cs low to write end 9 10 ns t aw address set-up to write end 9 10 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 1 1 ns t pwe we pulse width 10 12 ns t sd data set-up to write end 7 8 ns t hd data hold from write end 1 1 ns t lzwe we high to low z 3 3 ns t hzwe we low to high z [5] 0 7 0 8 ns shaded area contains advance information. notes: 3. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 4. at any given temperature and voltage condition, t hzcs is less than t lzcs for any given device. these parameters are guaranteed and not 100% tested. 5. t hzcs and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads and waveforms. transition is measured 500 mv from steady-state voltage. 6. the internal write time of the memory is defined by the overlap of cs low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write.
cym1851v33 preliminary document #: 38-05268 rev. ** page 4 of 9 switching characteristics over the operating range [3] (continued) 1851v33-20 1851v33-25 1851v33-35 parameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 20 25 35 ns t aa address to data valid 20 25 35 ns t oha data hold from address change 3 3 3 ns t acs cs low to data valid 20 25 35 ns t doe oe low to data valid 12 15 18 ns t lzoe oe low to low z 0 0 0 ns t hzoe oe high to high z 10 12 15 ns t lzcs cs low to low z [4] 3 3 3 ns t hzcs cs high to high z [4, 5] 10 12 15 ns t pd cs high to power-down 20 25 35 ns write cycle [6] t wc write cycle time 20 25 35 ns t scs cs low to write end 17 20 30 ns t aw address set-up to write end 17 20 30 ns t ha address hold from write end 3 3 3 ns t sa address set-up to write start 2 2 2 ns t pwe we pulse width 15 20 30 ns t sd data set-up to write end 12 15 20 ns t hd data hold from write end 2 2 2 ns t lzwe we high to low z 3 3 3 ns t hzwe we low to high z [5] 0 12 0 12 0 15 ns switching waveforms notes: 7. we is high for read cycle. 8. device is continuously selected, cs = v il , and oe = v il . read cycle no. 1 previous data valid data valid t rc t aa t oha address data out [7,8]
cym1851v33 preliminary document #: 38-05268 rev. ** page 5 of 9 note: 9. address valid prior to or coincident with cs transition low. switching waveforms (continued) read cycle no. 2 data valid t rc t acs t doe t lzoe t lzcs high impedance t hzoe t hzcs high impedance data out oe cs v cc supply current 50% 50% t pu icc isb t pd [7,9] write cycle no. 1 (we controlled) t wc data valid data undefined high impedance t scs t aw t sa t pwe t ha t hd t hzwe t lzwe t sd cs we address data in data out [6]
cym1851v33 preliminary document #: 38-05268 rev. ** page 6 of 9 note: 10. if cs goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) write cycle no. 2 (cs controlled) t wc data valid data undefined high impedance t scs t aw t pwe t ha t hd t hzwe t sd cs we address data in data out t sa [6,10] truth table cs we oe inputs/output mode h x x high z deselect/power-down l h l data out read l l x data in write l h h high z deselect ordering information speed (ns) ordering code package type package type operating range 12 cym1851v33pm-12c pm04 72-pin plastic simm module commercial cym1851v33p8-12c pm04 72-pin plastic simm module (gold contacts) cym1851v33pn-12c pn04 72-pin plastic angled simm module cym1851v33p6-12c pn04 72-pin plastic angled simm module (gold contacts) cym1851v33pz-12c pz09 72-pin plastic zip module 15 cym1851v33pm-15c pm04 72-pin plastic simm module commercial CYM1851V33P8-15C pm04 72-pin plastic simm module (gold contacts) cym1851v33pn-15c pn04 72-pin plastic angled simm module cym1851v33p6-15c pn04 72-pin plastic angled simm module (gold contacts) cym1851v33pz-15c pz09 72-pin plastic zip module shaded area contains advance information.
cym1851v33 preliminary document #: 38-05268 rev. ** page 7 of 9 20 cym1851v33pm-20c pm04 72-pin plastic simm module commercial cym1851v33p8-20c pm04 72-pin plastic simm module (gold contacts) cym1851v33pn-20c pn04 72-pin plastic angled simm module cym1851v33p6-20c pn04 72-pin plastic angled simm module (gold contacts) cym1851v33pz-20c pz09 72-pin plastic zip module 25 cym1851v33pm-25c pm04 72-pin plastic simm module commercial cym1851v33p8-25c pm04 72-pin plastic simm module (gold contacts) cym1851v33pn-25c pn04 72-pin plastic angled simm module cym1851v33p6-25c pn04 72-pin plastic angled simm module (gold contacts) cym1851v33pz-25c pz09 72-pin plastic zip module 35 cym1851v33pm-35c pm04 72-pin plastic simm module commercial cym1851v33p8-35c pm04 72-pin plastic simm module (gold contacts) cym1851v33pn-35c pn04 72-pin plastic angled simm module cym1851v33p6-35c pn04 72-pin plastic angled simm module (gold contacts) cym1851v33pz-35c pz09 72-pin plastic zip module ordering information (continued) speed (ns) ordering code package type package type operating range package diagrams 72-pin plastic simm module pm04 72-pin plastic angled simm module pn04
cym1851v33 preliminary document #: 38-05268 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 72-pin plastic zip module pz09
cym1851v33 preliminary document #: 38-05268 rev. ** page 9 of 9 document title: cym1851v33 1,024k x 32 3.3v static ram module document number: 38-05268 rev. ecn no. issue date orig. of change description of change ** 114168 3/19/02 dsg change from spec number: 38-m-00090 to 38-05268
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